1. Field of the Invention
The invention relates to an on-chip circuit unit to send electrical stimulus to other circuit units that are located on the same integrated circuit (IC) chip and a method for forming the same. More particularly, the invention relates to an on-chip voltage-regulating circuit or a voltage converter to send electrical power to other circuit units located on the same chip by way of a coarse conductor deposited over the passivation layer.
2. Brief Description of the Related Art
Today many electronic devices are required to run at high speed and/or low power consumption conditions. Moreover, a modern electronic system, module, or circuit board contains many different types of chips, such as Central Processing Units (CPUs), Digital Signal Processors (DSPs), analog chips, DRAMs, SRAMs, Flashs and etc. Each chip is fabricated using different types and/or different generations of IC manufacturing process technologies. For example, in a modern notebook personal computer, the CPU chip may be fabricated using an advanced 65 nm technology with power supply voltage at 1.2 V, the analog chip fabricated using a 0.25 um IC process technology with power supply voltage at 3.3 V, and the DRAM chip using a 90 nm IC process technology at 1.5V, and the flash chip using a 0.18 um technology with power supply voltage at 2.5V. With varieties of supply voltages in a single system, the on-chip voltage converter and/or voltage regulator become desirable. The DRAM chip may require an on-chip voltage converter and/or voltage regulator to convert 3.3V to 1.5V and the flash chip may also require an on-chip voltage converter to convert 3.3V to 2.5V. Moreover, the on-chip voltage converter or regulator should provide a constant voltage for the semiconductor devices located at different locations on an IC chip through on-chip power/ground buses. In this regard, an on-chip voltage regulator or an on-chip voltage converter affiliated with low parasitic power/ground lines is desired. In addition to the minimized energy consumption, the rippling effect that may occur in accordance with fluctuation of load capacitance and resistance is also abated.
U.S. Pat. No. 6,495,442 B1 by Lin and et al. describes post-passivation schemes on top of IC chips. The post-passivation scheme over the IC passivation layer is used as the global, power, ground, or signal distribution networks. The power/ground voltage is supplied from an external (outside of the chip) power supply source.
U.S. Pat. No. 6,649,509 B1 by Lin and et al. describes an embossing process to form post-passivation interconnection scheme over the IC passivation layer to be used as the global distribution network for power, ground, clock and/or signal.